Conventional digital integrated circuits comprise complex combinational networks for performing logical operations on data, and memory elements interconnected with the combinational networks to provide memory functions essential to the operation of the combinational networks. Such integrated circuits are difficult to test due to the complexity of their operation.
Modern digital integrated circuit designers incorporate test features in digital integrated circuits at the design stage to ensure that such circuits are testable. In one design technique, known as Level Sensitive Scan Design (LSSD), designers partition circuits into combinational networks and scannable memory elements, usually flip-flops. The flip-flops are made reconfigurable from their operating configuration (in which they are connected to the combinational networks of the circuit is required to support normal operation of the circuit) to as scan configuration in which they are decoupled from the combinational networks and connected in series to form one or more shift registers known as a "scan chains".
The scan configuration is used during testing of the circuit to shift a known test stimulus pattern into the scan chains. The flip-flops are then put into the operating configuration for one or more clock cycles so that combinational networks perform logical operations on some of the data making up the test stimulus pattern and alter the data stored in some of the flip-flops. The flip-flops are then returned to the scan configuration to shift the altered data out of the scan chains as test response patterns. The test response patterns are compared with calculated test response patterns or with test response patterns obtained from a circuit which is known to be functioning properly to determine whether the circuit under test is functioning properly.
The known test stimulus pattern may be a random pattern supplied by a random pattern generator which is internal or external to the digital system under test. The random pattern may even be generated within the scan chain by configuring the scan chain as a linear feedback shift register (LFSR) (see for example Konemann et al, IEEE Journal of Solid State Circuits, Vol. SC-15, No. 3, p. 315-319, June 1980).
Conventional random pattern scan testing can require very large numbers of random patterns for an acceptable level of fault coverage. Most faults can be detected by any one of several random patterns and these faults are usually detected during the early stages of random pattern testing. However a smaller number of faults can only be detected by very specific test patterns, and many more random patterns must be applied to ensure that these specific patterns are applied.
In a hybrid test approach, random pattern testing can be combined with stored pattern testing, the random patterns being used for detection of easily detected faults with a relatively small number of random patterns and the stored patterns being used for detection of faults which require very specific patterns for detection. Unfortunately, the number of stored patterns required for acceptable fault coverage can be very large even when stored pattern testing is combined with random pattern testing, so that test apparatus having very large storage capacity is needed.
In another hybrid test approach, random pattern testing can be combined with "biased" or "weighted" random pattern testing. "Weighted" random patterns (WRP) are patterns in which one logic state occurs more frequently than another logic state, the "weight" of the pattern being the ratio of occurrences of one logic state (e.g. the "1" state) to the other state (e.g. the "0" state). WRP testing can significantly reduce the number of test patterns needed for acceptable fault coverage.
Unfortunately, known on-chip WRP generators are significantly more complicated and consume significantly more area than uniform random pattern generators. Consequently the cost overhead of implementing a WRP builtin self test (BIST) strategy is relatively high.